L5953_07 datasheet(8/31 Pages) STMICROELECTRONICS

8 / 31 page

Block diagram and electrical specifications

L5953

8/31

N.C.

Not connected

GND

Ground

VSW

Source of the external MOS

GATEIN

Gate of the internal MOS

GATEOUT

Switching output for power mos gate

STRAP

Bootstrap

SYNC

Synchronization

VLR

REG2 linear voltage regulator output

VIN

REG2 linear voltage regulator input

FBLR

REG2 linear voltage regulator feedback

COMP

PWM compensation

PWM feedback

STCAP

ST-CAP

VSPI

Supply voltage for SPI I/O

VSTBY

REG1 stand-by linear voltage regulator output

ADJ

3.3V/5V REG1 voltage select

Table 4.

PIN function (continued)

Pin number

Pin name

Function

Table 5.

Electrical characteristics (Tamb = 25°C, VDD = 14.4V)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

IQ,STBY

Quiescent current with regulators

and high-side drivers off

W1, W2, RES, IRQ, not active;

REG2, HSD1, HSD2, PWM off;

S, C, D fixed at high/low logic

level

100

μA

Tsd

Thermal shutdown junction

temperature

150

°C

SMPS.PWM (Tamb = 25°C, VDD = 14.4V, Vo = 5V; unless otherwise specified.)

Vo,min

Minimum output voltage

Io = 200mA

2.4

2.5

2.6

Vo,max

Maximum output voltage

Io = 200mA

9.6

10.4

Vref,PWM

Voltage reference

1.275

Input voltage range

Vo = 5V; Io = 0.5A

ΔV

Line regulation

Io = 0.5A

100

ΔV

Load regulation

Vo = 5V; Io = 0.2A to 0.5A

Dropout voltage between Pin 19

and Pin 23

Io = 0.5A, Vo = 5V

0.5

Io = 1A, Vo = 5V

ILim

Current limit

1.2

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