SPI interface

L5953

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4

SPI interface

4.1

Signals description

The SPI interface available inside L5953 is able to work both in Mode 0 and Mode 3.

Serial output (Q). The output pin is used to transfer data serially out of the L5953. Data is

shifted out on the falling edge of the serial clock.

Serial input (D). The input pin is used to transfer data serially into the device. It receives

instructions, addresses, and data to be written. Input is latched on the rising edge of the

serial clock.

Serial clock (C). The serial clock provides the timing of the serial interface. Instructions,

addresses, or data present at the input pin are latched on the rising edge of the clock input,

while data on the Q pin changes after the falling edge of the clock input.

Chip select (S). This input is used to select the L5953. The chip is selected by a high to low

transition on the S pin. At any time, the chip is deselected by a low to high transition on the S

pin. As soon as the chip is deselected, the Q pin is at high impedance state. The pin allows

multiple L5953 to share the same SPI bus. After power up, the chip is at the deselect state.

SPI Input/Output are supplied by an external supply voltage VSPI while the core is supplied

by the stand-by regulator VSTBY. The SPI is reset by an internal signal whose buffered

version is RES. (See

Figure 12.)

4.2

Operations

All instructions, addresses and data are shifted in and out of the chip MSB first. Data input

(D) is sampled on the first rising edge of clock (C) after the chip select (S) goes low. Prior to

any operation, a one-byte instruction code must be entered in the chip. This code is entered

in the chip. This code is entered via the data input (D), and latched on the rising edge of the

clock input (C). To enter an instruction code, the product must have been previously

selected (S = low). Table 1 shows the instruction set and format for device operation. An

invalid instruction (one not contained in table 1) leaves the chip as previously selected.

4.3

Write enable (WREN and write disable (WRDI))

The L5953 contains a write enable latch. This latch must be set prior to every WRITE

operation. The WREN instruction will set the latch and the WRDI instruction will reset the

latch. The latch is reset under all the following conditions:

–– Power on

–

– WRDI instruction executed

As soon as the WREN or WRDI instruction is received by the L5953, the circuit executes the

instruction and enters a wait mode until it is deselected.