M48T02, M48T12

Operation modes

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2

Operation modes

As Figure 3 on page 6 shows, the static memory array and the quartz controlled clock

oscillator of the M48T02/12 are integrated on one silicon chip. The two circuits are

interconnected at the upper eight memory locations to provide user accessible

BYTEWIDE™ clock information in the bytes with addresses 7F8h-7FFh. The clock locations

contain the year, month, date, day, hour, minute, and second in 24 hour BCD format.

Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made

automatically.

Byte 7F8h is the clock control register. This byte controls user access to the clock

information and also stores the clock calibration setting.

The eight clock bytes are not the actual clock counters themselves; they are memory

locations consisting of BiPORT™ READ/WRITE memory cells. The M48T02/12 includes a

clock control circuit which updates the clock bytes with current information once per second.

The information can be accessed by the user in the same manner as any other location in

the static memory array.

The M48T02/12 also has its own Power-fail Detect circuit. The control circuitry constantly

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the

approximately 3V, the control circuitry connects the battery which maintains data and clock

operation until valid power returns.

Table 2.

Operating modes

Note:

2.1

Read mode

The M48T02/12 is in the READ Mode whenever W (WRITE Enable) is high and E (Chip

Enable) is low. The device architecture allows ripple-through access of data from eight of

16,384 locations in the static storage array. Thus, the unique address specified by the 11

Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data

address input signal is stable, providing that the E and G access times are also satisfied. If

the E and G access times are not met, valid data will be available after the latter of the Chip

Mode

E

G

W

DQ0-DQ7

Power

Deselect

4.75 to 5.5V

or

4.5 to 5.5V

X

X

High Z

Standby

WRITE

Active

READ

Active

READ

High Z

Active

Deselect

(1)

1.

See Table 11 on page 20 for details.

X

X

X

High Z

CMOS Standby

Deselect

≤ VSO(1)

X

X

X

High Z

Battery Back-up Mode