Clock operations

M48T02, M48T12

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'1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a

64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second

either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into

the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is

loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator

cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of

adjustment per calibration step in the calibration register. Assuming that the oscillator is in

fact running at exactly 32,768Hz, each of the 31 increments in the Calibration Byte would

represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –

2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M48T02/12 may

require. The first involves simply setting the clock, letting it run for a month and comparing it

to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows

the designer to give the end user the ability to calibrate his clock as his environment may

require, even after the final product is packaged in a non-user serviceable enclosure. All the

designer has to do is provide a simple utility that accesses the Calibration Byte.

The second approach is better suited to a manufacturing environment, and involves the use

of some test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit

in the Day Register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB (DQ0)

of the Seconds Register will toggle at 512 Hz. Any deviation from 512 Hz indicates the

degree and direction of oscillator frequency shift at the test temperature. For example, a

reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –

10 (WR001010) to be loaded into the Calibration Byte for correction.

Note:

Setting or changing the Calibration Byte does not affect the Frequency Test output

frequency. The device must be selected and addresses must be stable at Address 7F9

when reading the 512 Hz on DQ0.

The FT Bit must be set using the same method used to set the clock: using the WRITE Bit.

The LSB of the Seconds Register is monitored by holding the M48T02/12 in an extended

READ of the Seconds Register, but without having the READ Bit set. The FT Bit MUST be

reset to '0' for normal clock operations to resume.

Note:

It is not necessary to set the WRITE Bit when setting or resetting the Frequency Test Bit

(FT) or the Stop Bit (ST).

Calibration.”