M48T02 datasheet(9/24 Pages) STMICROELECTRONICS

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M48T02, M48T12

Operation modes

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2.2

Write mode

The M48T02/12 is in the WRITE Mode whenever W and E are active. The start of a WRITE

is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the

earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W

must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable

prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to

the end of WRITE and remain valid for tWHDX afterward. G should be kept high during

WRITE cycles to avoid bus contention; although, if the output bus has been activated by a

low on E and G, a low on W will disable the outputs tWLQZ after W falls.

Figure 5.

Write enable controlled, write AC waveform

Figure 6.

Chip enable controlled, write AC waveforms

AI01331

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A10

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI01332B

tAVAV

tEHAX

tDVEH

A0-A10

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

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