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STA335BWS 数据表(PDF) 59 Page - STMicroelectronics |
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STA335BWS 数据表(HTML) 59 Page - STMicroelectronics |
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59 / 68 page ![]() STA335BWS Register description 59/68 6.13 Variable max power correction registers (addr 0x27 to 0x28) MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. 6.14 Variable distortion compensation registers (addr 0x29 to 0x2A) DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1. 54 0x36 Channel 3, Post-scale C3PstS 0x7FFFFF 55 0x37 TWARN/OC - Limit TWOCL 0x5A9DF7 56 0x38 Channel 1, Mix 1 C1MX1 0x7FFFFF 57 0x39 Channel 1, Mix 2 C1MX2 0x000000 58 0x3A Channel 2, Mix 1 C2MX1 0x000000 59 0x3B Channel 2, Mix 2 C2MX2 0x7FFFFF 60 0x3C Channel 3, Mix 1 C3MX1 0x400000 61 0x3D Channel 3, Mix 2 C3MX2 0x400000 62 0x3E Unused 63 0x3F Unused Table 31. RAM block for biquads, mixing, scaling and bass management Index (Decimal) Index (Hex) Coefficient Default D7 D6 D5 D4 D3 D2 D1 D0 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 00 01 101 0 D7 D6 D5 D4 D3 D2 D1 D0 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 11 00 000 0 D7 D6 D5 D4 D3 D2 D1 D0 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 11 11 001 1 D7 D6 D5 D4 D3 D2 D1 D0 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 00 11 00 11 |
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