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STA335BWS 数据表(PDF) 17 Page - STMicroelectronics |
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STA335BWS 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 68 page  STA335BWS Electrical specifications 17/68 3.5 Power-on sequence Table 7. Power-on sequence Where: TR = minimum time between XTI master clock stable and Reset removal: 1 ms TC = minimum time between Reset removal and I2C program, sequence start: 1msec Note: Clock stable means: fmax - fmin < 1 MHz Note: No specific VCC and VDD_Dig turn −on sequence is required 3.6 Testing 3.6.1 Functional pin status Don’t care Don’t care CMD0 CMD1 CMD2 VCC VDD_Dig XTI Reset I2C PWDN TR TC Don’t care Don’t care CMD0 CMD1 CMD2 VCC VDD_Dig XTI Reset I2C PWDN TR TC Don’t care Don’t care Don’t care CMD0 CMD1 CMD2 VCC VDD_Dig XTI Reset I2C PWDN TR TC Don’t care Don’t care CMD0 CMD1 CMD2 VCC VDD_Dig XTI Reset I2C PWDN TR TC Don’t care Don’t care CMD0 CMD1 CMD2 VCC VDD_Dig XTI Reset I2C PWDN TR TC Don’t care Table 8. Functional pin status Pin name Pin # Logic value IC status PWRDN 23 0 Low absorption PWRDN 23 1 Normal operation TWARN 20 0 From external power stage is indicated a temperature warning TWARN 20 1 Normal operation EAPD 19 0 Low absorption for power stage All internal regulators are switched off EAPD 19 1 Normal operation |
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