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STA335BWS 数据表(PDF) 42 Page - STMicroelectronics |
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STA335BWS 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 68 page  Register description STA335BWS 42/68 6.7 Volume control registers (addr 0x06 to 0x0A) 6.7.1 Mute/line output configuration register Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs. 6.7.2 Master volume register 6.7.3 Channel 1 volume 6.7.4 Channel 2 volume D7 D6 D5 D4 D3 D2 D1 D0 LOC1 LOC0 Reserved C3M C2M C1M MMUTE 00 000 0 LOC[1:0] Line output configuration 00 Line output fixed - no volume, no EQ 01 Line output variable - CH3 volume effects line output, no EQ 10 Line output variable with EQ - CH3 volume effects line output D7 D6 D5 D4 D3 D2 D1 D0 MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0 11 11 11 11 D7 D6 D5 D4 D3 D2 D1 D0 C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0 01 10 00 00 D7 D6 D5 D4 D3 D2 D1 D0 C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 01 10 000 0 |
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