STA335BWS datasheet(41/68 Pages) STMICROELECTRONICS

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STA335BWS

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6.6.3

Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

6.6.4

LRCK double trigger protection

Actively prevents double trigger of LRCLK.

6.6.5

Auto EAPD on clock loss

When active, issues a power device power down signal (EAPD) on clock loss detection.

6.6.6

IC power down

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

to power down the power-stage, then the master clock to all internal hardware expect the

I2C block is gated. This places the IC in a very low power consumption state.

6.6.7

External amplifier power down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed on a low-power state (disabled). This

Bit

R/W

RST

Name

Description

R/W

BCLE

Binary output mode clock loss detection enable

Bit

R/W

RST

Name

Description

R/W

LDTE

LRCLK double trigger protection enable

Bit

R/W

RST

Name

Description

R/W

ECLE

Auto EAPD on clock loss

Bit

R/W

RST

Name

Description

7R/W

PWDN

0: IC power down low-power condition

1: IC normal operation

Bit

R/W

RST

Name

Description

R/W

EAPD

0: External power stage power down active

1: Normal operation

STA335BWS 数据表(PDF) 41 Page - STMicroelectronics

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