STV2310 datasheet(17/112 Pages) STMICROELECTRONICS

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STV2310

Functional Description

The Output Sync Pulse (H, V and F) can be embedded in the digital output stream, according to the

ITU_R BT_656/601 format, using the EAV and SAV codes. The Output Sync Pulse can also be

delivered on dedicated external pins (33, 34, 35). These pins can be used specifically if the output

sync pulses are no longer compliant with the ITU_R BT_656/601 format, as non-interlaced pictures

or signals from a non-standard source (VCR). See Section 4.12.2.1 and Section 4.12.2.2 for more

information.

4.2.2

Programming

The circuit can function in Automatic mode or use a programmable HPLL time constant. Automatic

mode is selected by default. In this case the STV2310 automatically adapts the time constant to the

reception conditions. In the case of unstable sources (such as VCRs) the circuit uses a special

user-programmable VCR time constant. This HPLL time constant's proportional gain is selected in

the HSYN_GP[7:0] bits in the DDECCONT26 register. The value for the integral gain is selected in

the HSYN_GI[7:0] bits in the DDECCONT27 register. These bits also define the programmable time

constant when the HTIMECSTSEL bit is reset in the DDECCONT22 register (Automatic mode

disabled).

To be automatically selected, the VCR time constant requires that the noise level be below the

noise threshold selected by the NOISE_THRESHOLD[2:0] bits in the DDECCONT25 register.

The Vsync search and initial Free-running modes are selected by the 5060MODE[1:0] bits in the

DDECCONT0 register.

The (fluctuating) average sync bottom and blanking level values, based on the Hsync Pulse Bottom

Period and Composite Video Burst Period identification data, are necessary in turn to perform the

clamp correction on the CVBS signal in the analog domain. (See Figure 9.) The clamp level is

programmed by the BLANKMODE[1:0] bits in the DDECCONT1 register.

The Active Input Video Period and small amplitude signals for the Active Input Video Period levels

which control the gain level of the AGC are programmed in the ACTITH[1:0] and SMHITH[1:0] bits

(respectively) in the DDECCONT16 register.

The CVBS saturation threshold is programmed in the SATLMTPT[1:0] and SATLMTLN[1:0] bits of

the DDECCONT16 register in the event of a high level of chroma demodulation. It is expressed as

a number of samples per field (when, according to the algorithm, the number of samples is reached,

the gain is decreased).

Output mode can be forced to 50 Hz or 60 Hz by 5060MODE[1:0] bits in the the DDECCONT00

To output a non-interlaced image, the chip must be set in direct parity mode by the DIRECTPARITY

bit in the DDECCONT1F register.

STV2310 数据表(PDF) 17 Page - STMicroelectronics

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