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STV2310 数据表(PDF) 47 Page - STMicroelectronics

部件名 STV2310
功能描述  Multistandard TV Digital Video Decoder with Adaptive Comb Filter and RGB/YCrCb Input
PDF  112 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STV2310 数据表(HTML) 47 Page - STMicroelectronics

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STV2310
Functional Description
UDW Coding for VPS
In Video Programming Systems (VPS), a nibble split algorithm is applied. In all bytes, bit 6 is the
even parity check of bits 5 to 0. Bit 7 is the complement of bit 6.
The result of the VPS sliced information is providing 12 bytes of data, which are generated in the
following order:
VPUD00: This byte provides the LSB contents of VPS byte 5.
VPUD01: This byte provides the MSB contents of VPS byte 5.
SD[1:0]Sound bits
RR[1:0]R-Rating bits for flagging material not suitable for children.
RX[3:0]Reserved bits for future applications. Presently not defined.
VPUD10: This byte provides the LSB contents of VPS byte 11.
VPUD11: This byte provides the MSB contents of VPS byte 11.
ID[1:0]Identification of the address for this VPS line.
ADT[4:0]Announced day of transmission.
AMT[3]Announced month of transmission.
VPUD20: This byte provides the LSB contents of VPS byte 12.
VPUD21: This byte provides the MSB contents of VPS byte 12.
AMT[2:0]Announced month of transmission.
ASH[4]Announced start hour.
VPUD30: This byte provides the LSB contents of VPS byte 13.
Table 19: UDW Coding for VPS
ADF
DID
SDID
DC
VPUD
00
VPUD
01
VPUD
10
VPUD
11
VPUD
20
VPUD
21
VPUD
30
VPUD
31
VPUD
40
VPUD
41
VPUD
S0
VPUD
S1
CS
bit
7
65
432
10
0
0
RX3RX2
RX1RX0
bit
7
65
432
10
0
0
SD1
SD0
RR1
RR0
bit
7
65
432
10
0
0
ADT2
ADT1
ADT0
AMT3
bit
7
65
432
10
0
0
ID1
ID0
ADT4
ADT3
bit
7
65
432
10
0
0
ASH3
ASH2
ASH1
ASH0
bit
7
65
432
10
0
0
AMT2
AMT1
AMT0
ASH4
bit
7
65
432
10
0
0
ASM1
ASM0
NC3
NC2



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