STW5095 datasheet(21/73 Pages) STMICROELECTRONICS

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Functional description

STw5095

20/72

In Analog Mode STw5095 can handle two different stereo audio signals, so it can be used as

a front end for an external voice codec that does not include microphone preamplifiers and

power drivers: mic signal is sent through Microphone preamplifiers directly to line out drivers

(Transmit path), while Receive signal is sent through Line In amplifiers to the selected power

drivers.

4.14

Automatic Gain Control (AGC)

STw5095 provides a digital Automatic Gain Control in AD path. The circuit can control the

input gain at MIC preamplifier, Line In amplifier or both (bits ENAGCMIC and ENAGCLIN in

CR35). When one input is selected, the center gain value used for the input is fixed with bits

MICLG, MICRG, LINLG and LINRG in CR3 to CR6 (like in normal operation), then the AGC

circuit adds to all the gains a value in the range -10.5 dB to +10.5 dB (or, extended with bit

AGCRANGE in CR35, -21 dB to 21 dB), in order to obtain an average level at the digital

interface output in the range -6 dB to -30 dB (selected with bits AGCLEV in CR35). The

AGC added gain acts directly in the input gain, to avoid input saturation and improve S/N

ratio, so it cannot exceed the input gain range. When MIC and Line-In inputs are selected

simultaneously the control is performed on the sum of the two, preserving the balance fixed

with input gains. Different values for Attack and Decay constants can be selected,

depending on the kind of signal the AGC has to control (i.e. voice, music). The Attack and

Decay time constants are related to the AD data rate (see bits AGCATT and AGCDEL in

CR34).

4.15

Interrupt request: IRQ pin

STw5095 interrupt request feature can signal to a control device the occurrence of particular

events. Two control registers are used to choose the behavior of IRQ pin: the first is a

Status/Event Register (CR32), where bits can represent the status of an internal function

(i.e. a voltage is above or below a threshold) or an event (i.e. a voltage changed crossing a

threshold); the second is a Mask Register (CR31) where if a bit in the mask is set to 1 then

the corresponding bit in the Status/Event Register can affect IRQ pin status.

The IRQ pin is always active low. At VCC power up an interrupt request is generated by the

Power-On-Reset circuit that sets to 1 bits PORMSK in CR31 and POREV in CR32. After this

event the PORMSK bit should be cleared by the user and bit IRQCMOS in CR33 should be

set according to the application (open drain or CMOS).

When an IRQ event occurs and SPI control interface is selected with no serial output pin it is

still possible to identify the event (and relative status) that generated the interrupt request.

This can be done by setting the IRQ mask/enable bits (in CR31) one at the time (with

successive writings) and reading the IRQ pin status. A simple example of this is the headset

plug-in detection: at first we set bit HSDETMSK=1 in CR31 (with all the other bits set to 0). If

there is an interrupt request then we set HSDETMSK=0 and HSDETEN=1, so we can read

the HSDET status at IRQ pin. Then we read CR32 to clear its content (even if no data is

sent out).

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