STPCE1EEBC datasheet(84/87 Pages) STMICROELECTRONICS

84 / 87 page

DESIGN GUIDELINES

84/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

PCI clocks

Measure PCICLKO:

- maximum is 33MHz by standard

- check it is at selected frequency

- it is generated from HCLK by a division

(1/2, 1/3 or 1/4)

Check PCICLKI equals PCICLKO

Verify PCICLKO loops to PCICLKI.

Verify maximum skew between any PCI clock

branch is below 2ns.

In Synchronous mode, check MCLKI.

Memory

clocks

Measure MCLKO:

- use a low-capacitance probe

- maximum is 100MHz

- check it is at selected frequency

- In SYNC mode MCLK=HCLK

- in ASYNC mode, default is 66MHz

Check MCLKI equals MCLKO

Verify load on MCLKI.

Verify MCLK programming (BIOS setting).

SYSRSTO#

Measure SYSRSTO# of STPC

See

Figure 4-3 for waveforms.

Verify SYSRSTI# duration.

Verify SYSRSTI# has no glitch

Verify clocks are running.

PCI cycles

Check PCI signals are toggling:

- FRAME#, IRDY#, TRDY#, DEVSEL#

- these signals are active low.

Check, with a logic analyzer, that first

PCI cycles are the expected ones:

memory read starting at address with

lower bits to 0xFFF0

Verify PCI slots

If the STPC don’t boot

- verify data read from boot memory is OK

- ensure Flash is correctly programmed

- ensure CMOS is cleared.

ISA

cycles

boot memory

Check RMRTCCS# & MEMRD#

Check directly on boot memory pin

Verify MEMCS16#:

- must not be asserted for 8-bit memory

Verify IOCHRDY is not be asserted

Verify ISAOE# pin:

- it controls IDE / ISA bus demultiplexing

Local Bus

cycles

boot memory

Check FCS0# & PRD#

Check directly on boot memory pin

Verify HCLK speed and CPU clock mode.

Check, with a logic analyzer, that first

Local Bus cycles are the expected one:

memory read starting at the top of boot

memory less 16 bytes

If the STPC don’t boot

- verify data read from boot memory is OK

- ensure Flash is correctly programmed

- ensure CMOS is cleared.

The CPU fills its first cache line by fetching 16 bytes from boot memory.

Then, first instructions are executed from the CPU.

Any boot memory access done after the first 16 bytes are due to the instructions executed by the CPU

=> Minimum hardware is correctly set, CPU executes code.

Please have a look to the Bios Writer’s Guide or Programming Manual to go further with your board testing.

Check:

How?

Troubleshooting

STPCE1EEBC 数据表(PDF) 84 Page - STMicroelectronics

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