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STPCE1EEBC 数据表(PDF) 52 Page - STMicroelectronics |
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STPCE1EEBC 数据表(HTML) 52 Page - STMicroelectronics |
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52 / 87 page  ELECTRICAL SPECIFICATIONS 52/87 Release 1.3 - January 29, 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 4.5.9 JTAG INTERFACE Figure 4-12 and Table 4-15 list the AC characteristics of the JTAG interface. Figure 4-12. JTAG timing diagram Table 4-15. JTAG AC Timings Name Parameter Min Max Unit Treset TRST pulse width 1 Tcycle Tcycle TCLK period 400 ns TCLK rising time 20 ns TCLK falling time 20 ns Tjset TMS setup time 200 ns Tjhld TMS hold time 200 ns Tjset TDI setup time 200 ns Tjhld TDI hold time 200 ns Tjout TCLK to TDO valid 30 ns Tpset STPC pin setup time 30 ns Tphld STPC pin hold time 30 ns Tpout TCLK to STPC pin valid 30 ns TCK STPC.input TRST Treset Tcycle STPC.output TMS,TDI TDO Tjset Tjhld Tjout Tpset Tphld Tpout |
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