STPCE1EEBC datasheet(16/87 Pages) STMICROELECTRONICS

16 / 87 page

PIN DESCRIPTION

16/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

2.2. SIGNAL DESCRIPTIONS

2.2.1. BASIC CLOCKS AND RESETS

SYSRSTI# System Reset/Power good. This input

is low when the reset switch is depressed.

Otherwise, it reflects the power supply’s power

good signal. This input is asynchronous to all

clocks, and acts as a negative active reset. The

reset circuit initiates a hard reset on the rising

edge of this signal.

SYSRSTO#

Reset Output to System. This is the

system reset signal and is used to reset the rest of

the components (not on Host bus) in the system.

The ISA bus reset is an externally inverted

buffered version of this output and the PCI bus

reset is an externally buffered version of this

output.

XTALI

14.3 MHz Crystal Input

XTALO 14.3 MHz Crystal Output. These pins are

provided for the connection of an external 14.318

MHz crystal to provide the reference clock for the

internal frequency synthesizer, from which all

other clock signals are generated.

The 14.318 MHz series-cut fundamental (not

overtone) mode quartz crystal must have an

Equivalent Series Resistance (ESR, sometimes

referred to as Rm) of less then 50 Ohms (typically

8 Ohms) and a shunt capacitance (Co) of less

than 7 pF. Balance capacitors of 16 pF should

also be added, one connected to each pin.

In the event of an external oscillator providing the

master clock signal to the STPC Elite device, the

TTL signal should be connected to XTALI.

HCLK

Host Clock. This clock supplies the CPU

and the host related blocks. This clock can e

doubled inside the CPU and is intended to operate

in the range of 25 to 100 MHz. This clock in

generated internally from a PLL but can be driven

directly from the external system.

GP_CLK

General Purpose clock. This clock is

programmable and its frequency can be as high

as 135 MHz.

2.2.2. MEMORY INTERFACE

MCLKI Memory Clock Input. This clock is driving

the SDRAM controller. This input should be a

buffered version of the MCLKO when more than 4

SDRAM chips are used. Go to section 6.3 for

more details.

MCLKO

Memory Clock Output. This clock is

driving the SDRAM devices and is generated from

an internal PLL. The default value is 66 MHz.

CS#[2]/MA[11] Chip Select/ Bank Address This

pin is CS#[2] in the case when 16 Mbit devices are

used. For all other densities, it becomes MA[11].

CS#[3]/MA[12]/BA[1]

Chip

Select/

Memory

Address/ Bank Address This pin is CS#[3] in the

case when 16Mbit devices are used. For all other

densities, it becomes MA[12] when 2 internal

banks devices are used and BA[1] when 4 internal

bank devices are used.

MA[10:0]

Memory Address. Multiplexed row and

column address lines.

BA[0] Memory Bank Address.

CS#[1:0] Chip Select. These signals are used to

disable or enable device operation by masking or

enabling all SDRAM inputs except MCLK, CKE,

and DQM.

MD[63:0] Memory Data. This is the 64-bit memory

data bus. MD[40-0] are read by the device strap

option registers during rising edge of SYSRSTI#.

RAS#[1:0] Row Address Strobe. There are two

active-low row address strobe output signals. The

RAS# signals drive the memory devices directly

without any external buffering.

CAS#[1:0] Column Address Strobe. There are

two active-low column address strobe output

signals. The CAS# signals drive the memory

devices directly without any external buffering.

MWE#

Write Enable. Write enable specifies

whether the memory access is a read (MWE# = H)

or a write (MWE# = L).

DQM#[7:0] Data Mask. Makes data output Hi-Z

after the clock and masks the SDRAM outputs.

Blocks SDRAM data input when DQM active.

2.2.3. PCI INTERFACE

PCI_CLKI 33 MHz PCI Input Clock. This signal is

the PCI bus clock input and should be driven from

the PCI_CLKO pin.

PCI_CLKO 33 MHz PCI Output Clock. This is the

master PCI bus clock output.

AD[31:0] PCI Address/Data. This is the 32-bit

multiplexed address and data bus of the PCI. This

bus is driven by the master during the address

phase and data phase of write transactions. It is

driven by the target during data phase of read

transactions.

CBE#[3:0]

Bus Commands/Byte Enables. These

are the multiplexed command and byte enable

signals of the PCI bus. During the address phase

they define the command and during the data

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