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M30833FJGP 数据表(PDF) 57 Page - Renesas Technology Corp

部件名 M30833FJGP
功能描述  SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
PDF  94 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M30833FJGP 数据表(HTML) 57 Page - Renesas Technology Corp

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Page 57
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BCLK
ALE
18ns.max
-2ns.min
RD
18ns.max
-5ns.min
Hi-Z
DB
0ns.min
td(BCLK-ALE) th(BCLK-ALE)
td(BCLK-RD)
26ns.min(1)
tac2(RD-DB)(2)
CSi
td(BCLK-CS)
18ns.max(1)
ADi
18ns.max(1)
th(BCLK-AD)
-3ns.min
th(BCLK-CS)
-3ns.min
BHE
tcyc
td(BCLK-AD)
tac2(AD-DB)(2)
WR,WRL,
WRH
18ns.max
BCLK
CSi
18ns.max
ADi
18ns.max
-3ns.min
-3ns.min
tcyc
BHE
DBi
td(BCLK-WR)
ALE
18ns.max
-2ns.min
Vcc=5V
th(BCLK-RD)
th(RD-DB)
tsu(DB-BCLK)
th(RD-CS)
0ns.min
td(BCLK-CS)
td(BCLK-AD)
td(BCLK-ALE)
th(BCLK-AD)
th(BCLK-CS)
th(WR-CS)(3)
td(DB-WR)(3)
th(WR-DB)(3)
th(WR-AD)(3)
td(DB-WR)=(tcyc x n-20)ns.min
(n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states)
NOTES:
3. Varies with operation frequency:
Measurement conditions
• VCC=4.2 to 5.5V
• Input high and low voltage:
VIH=2.5V, VIL=0.8V
• Output high and low voltage:
VOH=2.0V, VOL=0.8V
th(BCLK-ALE)
Read Timing
Write Timing (written in 2 cycles with no wait state)
Memory Expansion Mode and Microprocessor Mode (with a wait state)
th(RD-AD)
tw(WR)(3)
th(BCLK-WR)
0ns.min
Notes :
1. Value guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency:
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states.)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states.)
-3ns.min
Figure 5.3 VCC=5V Timing Diagram (2)



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