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M30833FJGP 数据表(PDF) 59 Page - Renesas Technology Corp

部件名 M30833FJGP
功能描述  SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
PDF  94 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M30833FJGP 数据表(HTML) 59 Page - Renesas Technology Corp

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Page 59
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BCLK
DW
DB
MAi
Vcc=5V
RAS
CASL
CASH
Hi-Z
tac4(CAS-DB)(2)
18ns.max
th(BCLK-CAD)
-3ns.min
tcyc
td(BCLK-RAD)
tac4(RAS-DB)(2)
Row address
Column address
th(BCLK-RAD)
-3ns.min
18ns.max(1)
td(BCLK-CAD)
18ns.max(1)
td(BCLK-RAS)
18ns.max(1)
td(BCLK-CAS)
th(RAS-RAD)(2)
tRP(2)
tac4(CAD-DB)(2)
th(BCLK-RAS)
-3ns.min
th(BCLK-CAS)
-3ns.min
0ns.min
tsu(DB-BCLK)
26ns.min(1)
th(CAS-DB)
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
Read Timing
Memory Expansion Mode and Microprocessor Mode
(When accessing the DRAM area)
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for the following combinations.
td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)
2. Varies with operation frequency:
tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
Figure 5.5 VCC=5V Timing Diagram (4)



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