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M30833FJGP 数据表(PDF) 77 Page - Renesas Technology Corp |
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M30833FJGP 数据表(HTML) 77 Page - Renesas Technology Corp |
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77 / 94 page  Page 77 1 9 f o 6 0 0 2 , 1 3 . n a J 1 4 . 1 . v e R 1 4 1 0 - 3 1 0 0 B 3 0 J E R ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M BCLK DW DB MAi Vcc=3.3V RAS CASL CASH Hi-Z th(BCLK-DB) -7ns.min 18ns.max th(BCLK-CAD) 0ns.min tcyc td(BCLK-RAD) th(BCLK-RAD) 0ns.min 18ns.max td(BCLK-CAD) 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) tRP(1) 18ns.max td(BCLK-DW) tsu(DB-CAS)(1) th(BCLK-RAS) 0ns.min th(BCLK-CAS) -3ns.min th(BCLK-DW) 0ns.min Row address Column address NOTES: 1. Varies with operation frequency. th(RAS-RAD)=(tcyc/2-13)ns.min tRP=(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min Measurement Conditions: • VCC=3.0 to 3.6V • Input high and low voltage: VIH=1.5V, VIL=0.5V • Output high and low voltage: VOH=1.5V, VOL=1.5V Write Timing Memory Expansion Mode and Microprocessor Mode (With 2 wait states, when accessing the DRAM area) th(RAS-RAD)(1) Figure 5.14 VCC=3.3V Timing Diagram (5) |
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