4584 datasheet(49/157 Pages) RENESAS

49 / 157 page

Rev.3.00

2004.08.06

page 49 of 155

REJ03B0010-0300Z

4584 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

(1) A/D control register

• A/D control register Q1

selection of analog input pins. Set the contents of this register

through register A with the TQ1A instruction. The TAQ1 instruc-

tion can be used to transfer the contents of register Q1 to register

• A/D control register Q2

contents of this register through register A with the TQ2A instruc-

tion. The TAQ2 instruction can be used to transfer the contents of

• A/D control register Q3

clock. Set the contents of this register through register A with the

TQ3A instruction. The TAQ3 instruction can be used to transfer

the contents of register Q3 to register A.

(2) Operating at A/D conversion mode

The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.”

(3) Successive comparison register AD

10-bit digital data format. The contents of the high-order 8 bits of

this register can be stored in register B and register A with the

TABAD instruction. The contents of the low-order 2 bits of this reg-

ister can be stored into the high-order 2 bits of register A with the

TALA instruction. However, do not execute these instructions dur-

ing A/D conversion.

When the contents of register AD is n, the logic value of the com-

parison voltage Vref generated from the built-in DA converter can

be obtained with the reference voltage VDD by the following for-

mula:

Logic value of comparison voltage Vref

Vref =

✕ n

n: The value of register AD (n = 0 to 1023)

VDD

1024

(4) A/D conversion completion flag (ADF)

A/D conversion completion flag (ADF) is set to “1” when A/D con-

version completes. The state of ADF flag can be examined with the

skip instruction (SNZAD). Use the interrupt control register V2 to

select the interrupt or the skip instruction.

The ADF flag is cleared to “0” when the interrupt occurs or when

the next instruction is skipped with the skip instruction.

(5) A/D conversion start instruction (ADST)

A/D conversion starts when the ADST instruction is executed. The

conversion result is automatically stored in the register AD.

(6) Operation description

A/D conversion is started with the A/D conversion start instruction

(ADST). The internal operation during A/D conversion is as follows:

➀ When the A/D conversion starts, the register AD is cleared to

“00016.”

➁ Next, the topmost bit of the register AD is set to “1,” and the com-

parison voltage Vref is compared with the analog input voltage

VIN.

➂ When the comparison result is Vref < VIN, the topmost bit of the

> VIN, it is cleared to “0.”

The 4584 Group repeats this operation to the lowermost bit of the

version stops after 2 machine cycles + A/D conversion clock (31

µs

when f(XIN) = 6.0 MHz in XIN through mode, f(ADCK) = f(INSTCK)/

6) from the start, and the conversion result is stored in the register

AD. An A/D interrupt activated condition is satisfied and the ADF

flag is set to “1” as soon as A/D conversion completes (Figure 36).

Table 13 Change of successive comparison register AD during A/D conversion

Comparison voltage (Vref) value

Change of successive comparison register AD

At starting conversion

✼1: 1st comparison result

✼3: 3rd comparison result

✼9: 9th comparison result

✼2: 2nd comparison result

✼8: 8th comparison result

✼A: 10th comparison result

1st comparison

2nd comparison

3rd comparison

After 10th comparison

completes

✼1

-----

✼2

✼3

✼8

✼9

✼A

A/D conversion result

VDD

1024

-------------

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