4584 datasheet(29/157 Pages) RENESAS

29 / 157 page

Rev.3.00

2004.08.06

page 29 of 155

REJ03B0010-0300Z

4584 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

(4) Notes on External 0 interrupt

➀ Note [1] on bit 3 of register I1

When the input of the INT0 pin is controlled with the bit 3 of reg-

ister I1 in software, be careful about the following notes.

• Depending on the input state of the P30/INT0 pin, the external 0

interrupt request flag (EXF0) may be set when the bit 3 of regis-

ter I1 is changed. In order to avoid the occurrence of an

unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to

Figure 18 ➀) and then, change the bit 3 of register I1.

In addition, execute the SNZ0 instruction to clear the EXF0 flag

to “0” after executing at least one instruction (refer to Figure 18

➁).

Also, set the NOP instruction for the case when a skip is per-

formed with the SNZ0 instruction (refer to Figure 18 ➂).

; (✕✕✕02)

TV1A

; The SNZ0 instruction is valid ........... ➀

; (1✕✕✕2)

TI1A

; Control of INT0 pin input is changed

NOP

........................................................... ➁

SNZ0

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

........................................................... ➂

✕ : these bits are not used here.

Fig. 18 External 0 interrupt program example-1

➁ Note [2] on bit 3 of register I1

When the bit 3 of register I1 is cleared to “0” , the RAM back-up

mode is selected and the input of INT0 pin is disabled, be careful

about the following notes.

• When the input of INT0 pin is disabled (register I13 = “0”), set the

key-on wakeup function to be invalid (register K20 = “0”) before

system enters to the RAM back-up mode. (refer to Figure 19➀).

; (✕✕✕02)

TK2A

; Input of INT0 key-on wakeup invalid .. ➀

EPOF

POF

; RAM back-up

✕ : these bits are not used here.

Fig. 19 External 0 interrupt program example-2

➂ Note on bit 2 of register I1

When the interrupt valid waveform of the P30/INT0 pin is

changed with the bit 2 of register I1 in software, be careful about

the following notes.

• Depending on the input state of the P30/INT0 pin, the external 0

interrupt request flag (EXF0) may be set when the bit 2 of regis-

ter I1 is changed. In order to avoid the occurrence of an

unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to

Figure 20➀) and then, change the bit 2 of register I1.

In addition, execute the SNZ0 instruction to clear the EXF0 flag

to “0” after executing at least one instruction (refer to Figure

20➁).

Also, set the NOP instruction for the case when a skip is per-

formed with the SNZ0 instruction (refer to Figure 20➂).

; (✕✕✕02)

TV1A

; The SNZ0 instruction is valid ........... ➀

; (✕1✕✕2)

TI1A

; Interrupt valid waveform is changed

NOP

........................................................... ➁

SNZ0

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

........................................................... ➂

✕ : these bits are not used here.

Fig. 20 External 0 interrupt program example-3

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