STV1602A datasheet(9/22 Pages) STMICROELECTRONICS

9 / 22 page

EQUALIZER (VEE = -5V, TA =25

oC unless otherwise specified)

Symbol

Parameter

Test Conditions

Test Circuit

Min.

Typ.

Max.

Unit

VMAX

Equalizer Max. Input Voltage

Pins AIX, AIY

Figure 3

0.88

Vp-p

GMAX

Equalizer Max. Gain

CIN

Input Capacity

Pins AIX, freq = 100MHz

RIN

Input Resistance

Pins AIX, freq = 100MHz

Ω

Figure 1 : tr,tf,tc,td Definition

80%

20%

50%

t/2

PCK

EVR

PCK

Ω

STV1602A

0.1

µF

220

Ω

220

Ω

220

Ω

(-5V)

ECL line drivers or

ECL/TTL translators

Power save SW

Figure 2 :

A Suggested Parallel Clock / Data

Output Circuit

SYN pin guaranteed operation range.

SYNC pin and serial to parallel conversion operate

normally within the frequency and ambient tem-

perature ranges according to the following consid-

erations.

Reclocked output.

STV1602A may be used as a repeater. The re-

clocked output, providing characteristics almost

identical to the serial output of STV1601A is avail-

able from SX (Pin 4) and SY (Pin 3).

When the reclocked output is used, it is recom-

mended not to use simultaneously use the parallel

outputs (data and clock) in order to avoid possible

logic errors caused by an excessively high tem-

perature which may result from additional power

dissipation created by the reclocked output circuit

under certain environnmental conditions.

If, for the sake of a design convenience, both

reclocked and parallel outputs are to be used, the

ambient temperature has to be kept as low as

possible or, at least, the airflow around STV1602A

must be carefully considered. In addition, it is rec-

ommended to put 220

Ω resistors on all parallel

outputs including the clock as shown in Figure 2.

This reduces the magnitude of the spike current

resulting from the parallel output circuit inside the

chip and helps reduce the probability of logic errors

at high temperature.

Power saving in repeater mode

Since the parallell output is not always required for

a reclocked repeater, the chip has been designed

such that the uncessary parallel logic circuit can be

disabled by disconnecting Pin 8, one of VEEs, from

the power supply. With this arrangement the power

dissipation is reducible to about 45 percent of that

of the fully functional mode.

In practice, a test switch should be provided so that

some parallel signals may be available during ad-

justment procedures as shown in Figure 2.

STV1602A

9/22

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