Parallel clock

Parallel data

V

OH

V

OL

EVR output voltage

Figure 22 : Phase Relation of Parallel Clock, Data and EVR Voltage Level

21

19

18

9

EVR

PCK

D0

D9

1k

Ω

1k

Ω

1k

Ω

1k

Ω

V

EE

STV1602A

0.1

µF

Figure 23 : Parallel Clock Data Output Circuit

EVR

PCK

1k

Ω

1k

Ω

V

EE

STV1602A

0.1

µF

21

6

35

DPR

0.1

µF

CMOS inverter

10k

Ω

10k

Ω

Figure 24 : A Circuit Example to Disable Parallel

Clock

V

EE

10k

Ω

TN1

PCX

FV

Small signal

transistor

Frequency monitor

10

µF

22k

Ω

1k

Ω

STV1602A

636

19

Figure 25 : VCO Temperature Compensation

and Free Running Frequency Ad-

justment

8. VCO temperature compensation and oscil-

lation frequency adjustment.

VCO oscillation frequency depends on the tem-

perature as shown in Figures 29 and 30 ”Repre-

sentative characteristics example”. Within the

normal range of operation, frequency increases

with temperature.

FV pin voltage remains almost constant regardless

of temperature.

Figure 25 shows an example of a temperature

compensation circuit using a diode (transistor with

C-B diode short-circuited) and a resistor between

PLL pull-in range (signal frequency 270, 177 and

143MHz) are given by Figures 32, 33 and 34.

9. VCO free running frequency adjustment

VCO free running frequency adjustment is per-

formed at room temperature.

If TN1 is set High, VCO is free running. Wait for 5

to 10 minutes after turning power supply ON (warm

up time).

While monitoring PCK (Pin 19) output, adjust the

signal frequency (within

±1%) with the variable

STV1602A

18/22