STV1602A datasheet(17/22 Pages) STMICROELECTRONICS

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1 TV line

4:2:2 Data

Stream

SYN output

(case A)

SYN output

(case B)

SYN output

(case C)

Figure 20 : SYNC Output in 4:2:2 Case (not to scale)

1 TV line

SYN output

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4 fsc

DataStream

Figure 21 : SYNC Output in 4 fsc Case (not to scale)

Each time the sync word is detected, SYN (Pin 20)

changes state as shown in Figure 20.

When a receiver using STV1602A is properly im-

plemented and adjusted, the health of the imple-

mentation can be checked simply by looking at

SYN (Pin 20) output while an encoded signal is

present at the input.

SYN is an output of a flip-flop which togglesat each

detection of TRS at the SYNC detector. Since the

4:2:2 signal contains two kinds of TRSs, SAV and

EAV, when the output of SYN is observed by an

oscilloscope it looks like either case A or case B as

shown in Figure 20 depending upon the initial

condition of the Flip-Flop.

When bit erros are occurring somewhere in the

transmission path, SYN output is affected and

looks like as shown in case C.

Figure 21 illustrates the case for 4 fsc (D2 NTSC

and PAL).

Differing from the 4:2:2 case, SYN output has an

equal mark and space ratio due to the periodic

occurence (once per one TV line) of the TRS

detection. However, transmission path bit errors

will cause the SYN output to appear similar to the

4:2:2 case.

If SYN signal is used other than for monitoring

purposes, buffering similar to that of DPR is re-

quired due to the high impedance nature of SYN

output.

7. Phase relation ship between parallel data

and parallel clock

Parallel data and clock are output so that the rising

edge of the parallel clock is located at the center of

the parallel data. Both parallel data and clock

(nearly identical to that of single ECL) have DC

levels depending on the temperature. In order to

simplify the driving amplifier, a reference level

(EVR) is available at Pin 21. PCX, Dn and EVR use

pull down resistors (identical values). A peripheral

circuit example is shown in Figure 23. Figure 24

shows a circuit to disable the parallel clock output.

STV1602A

17/22

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