STV1602A datasheet(15/22 Pages) STMICROELECTRONICS

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Ω

Serial

AIX

AIY

STV1602A

Figure 12 : Equalizer Transformer Input Circuit

STV1602A

MON

GND

Ω coaxial cable

To 50

Ω input

oscilloscope

Ω

Figure 14 : Equalized Waveforms Monitoring

STV1602A

29 CX

µF/16V

2.2k

Ω

Figure 15 : AGC Time Constant

Coaxial

Cable

47pF

AIY

Pin 25

AIX

Pin 26

Terminator

1mm

Printed circuit inductance

R = 6mm

(

Through-holeto a ground plane)

Figure 13 : An example of technique to improve

the return-loss figure for the capaci-

tor coupling input case

In both input circuit configurations, a consideration

is required in a practical design to obtain a sufficient

return-loss (at least 15dB over a frequency range

of 5MHz to the bit rate frequency used). To achieve

this, it is effective to add a small inductance in

series with the 75

Ω termination resistor. Figure 13

shows an implementation example.

MON Pin (31)

Equalized signals can be observed at this pin by

connecting an oscilloscope input (50

Ω).

CX Pin (29) Equalizer AGC time constant

Connect a 10

µF capacitor in serial with 2.2kΩ

resistor between this pin and GND in order to obtain

stable operation at all times. According to input

signals, voltage changes from -2V to -2.4V can

occur.

2. Digital input

The serial data input can be used without the

equalizer.

DIX (Pin 33) and DIY (Pin 34) are differential inputs

for ECL signals.

From these pins, input signals are differentially

amplified, therefore with no input signals, the data

detectionsignals could go High and erroneous data

would be transferred to the parallel output.

To avoid this, a voltage level conforming to ECL

specifications must be applied between DIX and

DIY pins.

Also, while the analog input is in use, digital input

must be kept ”quiet” in order to avoid possible

errors caused by cross-talk. This cross-talk prob-

lem naturally gets most severe when the analog

input cable length is close to the limit of the trans-

mission capability.

3. Serial input selection

Selection of the serial input is performed by ADS

(Pin 32); when High the digital input is enabled; this

input can be used for very short transmission lines.

When Low, the equalizer input is enabled;this input

must be used for long transmission lines.

4. PLL

In order to extract clock signals from the equalized

serial data, it is processed to generate edge signals

which are sent to the phase comparator.

When the PLL is locked, the identifier clock (D -

flipflop) will be in phase with the incoming clock.

The identifier clock rises at the center of the data

period for easy identification.

The PLL detailed block diagram is shown in Fig-

ure 16.

ESI is the VCO control input (Pin 37). Normally, the

phase comparator output ESO (Pin 1) is connected

to ESI.

Since the VCO employed has a very high sensitiv-

ity, those two nodes must be connected with a

shortest distance and a minimum area of conductor

STV1602A

15/22

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