STV1602A datasheet(16/22 Pages) STMICROELECTRONICS

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Descrambler

NZRI to NRZ

conversion

Phase

Comparator

VCO

RSE

DIX DIN

ADS

TN1

ESO

ESI

From

equalizer

Figure 16 : Serial Data Input and PLL

on the printed circuit board. Encircling those two

nodes by a ground guarding is an efficient method

to prevent errors caused by an ”antenna effect”.

Through FV (Pin 35) one can adjust the free run-

ning frequency; when the FV Voltage is equal to

VEE, the free running frequency is the lowest; the

voltage adjustment can be performed by using a

variable resistor connected between FV and VEE.

RSE (Pin 22) selects the VCO frequency range;

High : 140 to 270MHz, Low : 100 to 145MHz.

When TN1 (Pin 6) is set High, input signals are

disabled and the VCO free runs. The capacitor

connected between TN1 and GND avoids mislock-

ing problem when the power supply is switched on.

Data detection

Serial data edges are detected and go through low

pass filter. The processed signal is available at

DPR (Pin 35).DPR goes High when an input signal

is detected, otherwise it stays Low.

The driving capability of this pin is weak. It is

recommended to load it with a high impedance

CMOS or equivalent.

5. NRZI To NRZ conversion, descrambler

Serial data delivered by the identifier is available in

differential mode, SX (Pin 4) and SY (Pin 3). At the

same time, to recover the original data, NRZI to

NRZ conversion and descrambling are performed.

PLL

Data

(NRZI)

Clock

Serial

Signal

Data (NRZ)

Figure 17 : NRZI to NRZ conversion

Out

Figure 18 : x

9 +x4 + 1 Descrambler

Out

D10

Figure 19 : Actual x

9 +x4 + 1 Descrambler

6. Serial to parallel conversion

After descrambling, serial data is sent to a 30-bit

sequence 111111111100000000000000000000is

detected, sync word detection signal is output, the

counter which divides the clock frequency by 10 is

initialized and data is converted to parallel (10-bit

word) to be output.

STV1602A

16/22

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