H8SLASH300H datasheet(82/552 Pages) RENESAS

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Section 3 Exception Handling

Rev. 3.00 May 15, 2007 Page 50 of 516

REJ09B0152-0300

3.4.4

Interrupt Flag Register 1 (IRR1)

IRR1 indicates the IRQAEC, IRQ1, and IRQ0 interrupt request status.

Bit

Bit Name

Initial

Value

R/W

Description

7 to 3



All 0



Reserved

The write value should always be 0.

IRREC2

R/(W)* IRQAEC Interrupt Request Flag

[Setting condition]

When the P12 pin is set to the IRQAEC/AECPWM pin

and the specified edge is detected as the pin state

[Clearing condition]

When 0 is written to this bit

IRRI1

R/(W)* IRQ1 Interrupt Request Flag

[Setting condition]

When the

IRQ1 pin is set as the interrupt input pin and

the specified edge is detected

[Clearing condition]

When 0 is written to this bit

IRRI0

R/(W)* IRQ0 Interrupt Request Flag

[Setting condition]

When the

IRQ0 pin is set as the interrupt input pin and

the specified edge is detected

[Clearing condition]

When 0 is written to this bit

Note:

Only 0 can be written to clear the flag.

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