H8SLASH300H datasheet(85/552 Pages) RENESAS

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Section 3 Exception Handling

Rev. 3.00 May 15, 2007 Page 53 of 516

REJ09B0152-0300

3.5.2

Internal Interrupts

Internal interrupts generated from the on-chip peripheral modules have the following features:

• For each on-chip peripheral module, there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts. Internal interrupts can be

controlled independently. If an enable bit is set to 1, an interrupt request is sent to the interrupt

controller.

3.6

Operation

NMI interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts and

on-chip peripheral module interrupts, an enable bit is provided for each interrupt. Clearing an

enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable

bits are set to 1 are controlled by the interrupt controller.

Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to

interrupt acceptance.

Interrupt operation is described as follows.

1. If an interrupt source whose interrupt enable register bit is set to 1 occurs, an interrupt request

is sent to the interrupt controller.

2. When the interrupt controller receives an interrupt request, it sets the interrupt request flag.

3. From among the interrupts with interrupt request flags set to 1, the interrupt controller selects

the interrupt request with the highest priority and holds the others pending (see table 3.1).

4. The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request

is accepted; if the I bit is 1, the interrupt request is held pending.

5. If the interrupt request is accepted, after processing of the current instruction is completed,

both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in

figure 3.5. The PC value pushed onto the stack is the address of the first instruction to be

executed upon return from interrupt handling.

6. The I bit of CCR is set to 1, masking further interrupts.

7. The vector address corresponding to the accepted interrupt is generated, and the interrupt

handling routine located at the address indicated by the contents of the vector address is

executed.

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