HD6417618A datasheet(409/646 Pages) RENESAS

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Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 377 of 610

REJ09B0131-0600

Start of initialization

Clear TE and RE bits

in SCSCR to 0

Set TFRST and RFRST bits

in SCFCR to 1 to clear

the FIFO buffer

After reading BRK, DR,

and ER flags in SCFSR

and a flag in SCLSR,

write 0 to clear them

Set CKE1 and CKE0 bits

in SCSCR (leaving TE, RE, TIE,

and RIE bits cleared to 0)

Set data transfer format

in SCSMR

Set value in SCBRR

1-bit interval elapsed?

Set RTRG1-0 and TTRG1-0 bits

in SCFCR, and clear TFRST

and RFRST bits to 0

Set TE and RE bits in SCSCR

to 1, and set TIE, RIE,

and REIE bits

End of initialization

Wait

Yes

Leave the TE and RE bits cleared

to 0 until the initialization almost

ends. Be sure to clear the TIE,

RIE, TE, and RE bits to 0.

Set the CKE1 and CKE0 bits.

Set the data transfer format in

SCSMR.

Write a value corresponding to

the bit rate into SCBRR. This

is not necessary if an external

clock is used. Wait at least one

bit interval after this write before

moving to the next step.

Set the TE or RE bit in SCSCR

to 1. Also set the TEI, RIE, and

REIE bits to enable the TxD,

RxD, and SCK pins to be used.

When transmitting, the TxD pin

will go to the mark state.

When receiving in clocked

synchronous mode with the

synchronization clock output (clock

master) selected, a clock starts to

be output from the SCIF_CLK pin

at this point.

[1]

[2]

[3]

[4]

[5]

[2]

[3]

[4]

[5]

Figure 14.12 Sample Flowchart for SCIF Initialization

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