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HD6417618A 数据表(PDF) 145 Page - Renesas Technology Corp |
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HD6417618A 数据表(HTML) 145 Page - Renesas Technology Corp |
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145 / 646 page ![]() Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 113 of 610 REJ09B0131-0600 7.4 Register Descriptions The BSC has the following registers. For the addresses and access size for these registers, see section 20, List of Registers. Do not access spaces other than CS0 until setting the memory interfaces is complete. • Common control register (CMNCR) • CS0 space bus control register for area 0 (CS0BCR) • CS3 space bus control register for area 3 (CS3BCR) • CS4 space bus control register for area 4 (CS4BCR) • CS5B space bus control register for area 5B (CS5BBCR) • CS6B space bus control register for area 6B (CS6BBCR) • CS0 space wait control register for area 0 (CS0WCR) • CS3 space wait control register for area 3 (CS3WCR) • CS4 space wait control register for area 4 (CS4WCR) • CS5B space wait control register for area 5B (CS5BWCR) • CS6B space wait control register for area 6B (CS6BWCR) • SDRAM control register (SDCR) • Refresh timer control/status register (RTCSR) • Refresh timer counter (RTCNT) • Refresh time constant register (RTCOR) |
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