H8SLASH3024F datasheet(49/841 Pages) RENESAS

49 / 841 page

Section 1 Overview

Rev. 2.00 Sep 20, 2005 page 11 of 800

REJ09B0260-0200

Pin No.

Type

Symbol

FP-100B

TFP-100B FP-100A I/O

Name and Function

System

control

RES

Input

Reset input: When driven low, this pin resets

the chip. This pin must be driven low at

power-up.

RESO

Output Reset output (On-chip mask ROM

versions): Outputs the reset signal generated

by the watchdog timer to external devices

FWE

Input

Write enable signal (On-chip flash memory

versions): Flash memory programming

control signal

STBY

Input

Standby: When driven low, this pin forces

a transition to hardware standby mode

BREQ

Input

Bus request: Used by an external bus

master to request the bus right

BACK

Output Bus request acknowledge: Indicates that

the bus has been granted to an external bus

master

Interrupts

NMI

Input

Nonmaskable interrupt: Requests a

nonmaskable interrupt

IRQ5 to

IRQ0

17, 16,

90 to 87

19, 18,

92 to 89

Input

Interrupt request 5 to 0: Maskable interrupt

request pins

Address

bus

A23 to A0

97 to 100,

56 to 45,

43 to 36

99, 100,

1, 2,

58 to 47,

45 to 38

Output Address bus: Outputs address signals

Data bus

D15 to D0

34 to 23,

21 to 18

36 to 25,

23 to 20

Input/

output

Data bus: Bidirectional data bus

Bus

control

CS7 to

CS0

2 to 5,

88 to 91

4 to 7, 90

to 93

Output Chip select: Select signals for areas 7 to 0

Output Address strobe: Goes low to indicate valid

address output on the address bus

Output Read: Goes low to indicate reading from the

external address space

HWR

Output High write: Goes low to indicate writing to the

external address space; indicates valid data

on the upper data bus (D15 to D8).

LWR

Output Low write: Goes low to indicate writing to the

external address space; indicates valid data

on the lower data bus (D7 to D0).

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