H8SLASH3024F datasheet(16/841 Pages) RENESAS

16 / 841 page

Rev. 2.00 Sep 20, 2005 page xvi of xxxviii

11.2.3 Reset Control/Status Register (RSTCSR)............................................................ 342

11.2.4 Notes on Register Access .................................................................................... 344

11.3

Operation .......................................................................................................................... 346

11.3.1 Watchdog Timer Operation ................................................................................. 346

11.3.2 Interval Timer Operation ..................................................................................... 347

11.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 347

11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 348

11.4

Interrupts........................................................................................................................... 349

11.5

Usage Notes ...................................................................................................................... 349

Section 12 Serial Communication Interface ................................................................ 351

12.1

Overview........................................................................................................................... 351

12.1.1 Features................................................................................................................ 351

12.1.2 Block Diagram..................................................................................................... 353

12.1.3 Pin Configuration ................................................................................................ 354

12.1.4 Register Configuration......................................................................................... 355

12.2

Register Descriptions........................................................................................................ 356

12.2.1 Receive Shift Register (RSR) .............................................................................. 356

12.2.2 Receive Data Register (RDR).............................................................................. 356

12.2.3 Transmit Shift Register (TSR) ............................................................................. 357

12.2.4 Transmit Data Register (TDR) ............................................................................ 357

12.2.5 Serial Mode Register (SMR) ............................................................................... 358

12.2.6 Serial Control Register (SCR) ............................................................................. 361

12.2.7 Serial Status Register (SSR) ................................................................................ 366

12.2.8 Bit Rate Register (BRR) ...................................................................................... 372

12.3

Operation .......................................................................................................................... 380

12.3.1 Overview.............................................................................................................. 380

12.3.2 Operation in Asynchronous Mode ....................................................................... 383

12.3.3 Multiprocessor Communication .......................................................................... 392

12.3.4 Synchronous Operation ....................................................................................... 399

12.4

SCI Interrupts.................................................................................................................... 408

12.5

Usage Notes ...................................................................................................................... 409

12.5.1 Notes on Use of SCI ............................................................................................ 409

Section 13 Smart Card Interface ..................................................................................... 415

13.1

Overview........................................................................................................................... 415

13.1.1 Features................................................................................................................ 415

13.1.2 Block Diagram..................................................................................................... 416

13.1.3 Pin Configuration ................................................................................................ 417

13.1.4 Register Configuration......................................................................................... 417

13.2

Register Descriptions........................................................................................................ 418

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