H8SLASH3024F datasheet(29/841 Pages) RENESAS

29 / 841 page

Rev. 2.00 Sep 20, 2005 page xxix of xxxviii

Figure 13.12 Retransmission in SCI Receive Mode ................................................................. 439

Figure 13.13 Retransmission in SCI Transmit Mode................................................................ 440

Section 14 A/D Converter

Figure 14.1

A/D Converter Block Diagram ............................................................................ 442

Figure 14.2

A/D Data Register Access Operation (Reading H'AA40) ................................... 450

Figure 14.3

Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ........ 452

Figure 14.4

Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2

Selected) .............................................................................................................. 454

Figure 14.5

A/D Conversion Timing ...................................................................................... 455

Figure 14.6

External Trigger Input Timing............................................................................. 456

Figure 14.7

Example of Analog Input Protection Circuit ....................................................... 458

Figure 14.8

Analog Input Pin Equivalent Circuit.................................................................... 458

Figure 14.9

A/D Converter Accuracy Definitions (1)............................................................. 460

Figure 14.10 A/D Converter Accuracy Definitions (2)............................................................. 460

Figure 14.11 Analog Input Circuit (Example) .......................................................................... 461

Section 15 D/A Converter

Figure 15.1

D/A Converter Block Diagram ............................................................................ 464

Figure 15.2

Example of D/A Converter Operation ................................................................. 469

Section 16 RAM

Figure 16.1

RAM Block Diagram........................................................................................... 472

Section 17 Flash Memory [H8/3026F-ZTAT Version]

Figure 17.1

Block Diagram of Flash Memory ........................................................................ 477

Figure 17.2

Flash Memory Related State Transitions ............................................................. 488

Figure 17.3

Reading Overlap RAM Data in User Mode/User Program Mode ....................... 491

Figure 17.4

Writing Overlap RAM Data in User Program Mode ........................................... 492

Figure 17.5

System Configuration When Using Boot Mode .................................................. 494

Figure 17.6

Boot Mode Execution Procedure ......................................................................... 495

Figure 17.7

RAM Areas in Boot Mode................................................................................... 497

Figure 17.8

Example of User Program Mode Execution Procedure ....................................... 500

Figure 17.9

FLMCR1 Bit Settings and State Transitions ....................................................... 502

Figure 17.10 Program/Program-Verify Flowchart (128-Byte Programming)........................... 507

Figure 17.11 Erase/Erase-Verify Flowchart (Single-Block Erasing) ........................................ 510

Figure 17.12 Flash Memory State Transitions (When High Level is Applied to FWE Pin

in Mode 5 or 7 (On-Chip ROM Enabled))........................................................... 514

Figure 17.13 Flowchart of Flash Memory Emulation in RAM................................................. 515

Figure 17.14 Example of RAM Overlap Operation .................................................................. 516

Figure 17.15 Memory Map in PROM Mode............................................................................. 519

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