H8SLASH3024F datasheet(9/841 Pages) RENESAS

9 / 841 page

Rev. 2.00 Sep 20, 2005 page ix of xxxviii

Contents

Section 1 Overview.............................................................................................................

1.1

Overview...........................................................................................................................

1.2

Block Diagram..................................................................................................................

1.3

Pin Description .................................................................................................................

1.3.1

Pin Arrangement..................................................................................................

1.3.2

Pin Functions .......................................................................................................

1.3.3

Pin Assignments in Each Mode ...........................................................................

1.4

Caution on Crystal Resonator Connection........................................................................

Section 2 CPU ...................................................................................................................... 19

2.1

Overview...........................................................................................................................

2.1.1

Features................................................................................................................

2.1.2

Differences from H8/300 CPU ............................................................................

2.2

CPU Operating Modes......................................................................................................

2.3

Address Space...................................................................................................................

2.4

Register Configuration......................................................................................................

2.4.1

Overview..............................................................................................................

2.4.2

General Registers.................................................................................................

2.4.3

Control Registers .................................................................................................

2.4.4

Initial CPU Register Values.................................................................................

2.5

Data Formats.....................................................................................................................

2.5.1

General Register Data Formats............................................................................

2.5.2

Memory Data Formats .........................................................................................

2.6

Instruction Set...................................................................................................................

2.6.1

Instruction Set Overview .....................................................................................

2.6.2

Instructions and Addressing Modes.....................................................................

2.6.3

Tables of Instructions Classified by Function......................................................

2.6.4

Basic Instruction Formats ....................................................................................

2.6.5

Notes on Use of Bit Manipulation Instructions ...................................................

2.7

Addressing Modes and Effective Address Calculation.....................................................

2.7.1

Addressing Modes ...............................................................................................

2.7.2

Effective Address Calculation .............................................................................

2.8

Processing States ..............................................................................................................

2.8.1

Overview..............................................................................................................

2.8.2

Program Execution State .....................................................................................

2.8.3

Exception-Handling State ....................................................................................

2.8.4

Exception Handling Operation ............................................................................

2.8.5

Bus-Released State ..............................................................................................

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