H8SLASH3024F datasheet(71/841 Pages) RENESAS

71 / 841 page

Section 2 CPU

Rev. 2.00 Sep 20, 2005 page 33 of 800

REJ09B0260-0200

Table 2.4

Arithmetic Operation Instructions

Instruction Size*

Function

ADD,SUB

B/W/L

Rd ± Rs

→ Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on

immediate data and data in a general register. (Immediate byte data cannot

be subtracted from data in a general register. Use the SUBX or ADD

instruction.)

ADDX,

SUBX

Rd ± Rs ± C

→ Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on data in two general

registers, or on immediate data and data in a general register.

INC,

DEC

B/W/L

Rd ± 1

→ Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands can

be incremented or decremented by 1 only.)

ADDS,

SUBS

Rd ± 1

→ Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

DAA,

DAS

Rd decimal adjust

→ Rd

Decimal-adjusts an addition or subtraction result in a general register by

referring to CCR to produce 4-bit BCD data.

MULXU

B/W

× Rs → Rd

Performs unsigned multiplication on data in two general registers:

either 8 bits

× 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

MULXS

B/W

× Rs → Rd

Performs signed multiplication on data in two general registers:

either 8 bits

× 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

H8/3024F 数据表(PDF) 71 Page - Renesas Technology Corp

H8/3024F 数据表(HTML) 71 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载