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Note: 3

This delay is necessary to avoid a wrong detection of polarity change in the case of a composite sync.

4

See Figure 10 for explanation of reference phase.

5

These parameters are not tested on each unit. They are measured during our internal qualification.

6

A larger range may be obtained by application.

7

When at 0xxx xxxx, (HMoiré/HLock not selected), Pin 3 is a DAC with 0.3...2.75V range. When at 1xxx xxxx

(HMoiré/HLock selected) and PLL1 is locked, Pin 3 provides the waveform for HMoiré. See also Moiré

section.

8

9

Duty Cycle is the ratio between the output transistor OFF time and the period. The scanning transistor is

controlled OFF when the output transistor is OFF.

10 Initial Condition for Safe Start Up.

2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION

FBth

Flyback Input Threshold Voltage (Pin 12)

0.65

0.75

V

Hjit

At 31.4kHz

70

ppm

HDmin

HDmax

Horizontal Drive Output Duty-Cycle (Pin

Sub-Address 00

Byte x1111111

30

65

%

%

XRAYth

X-RAY Protection Input Threshold Volt-

age,

Pin 25, (see fig. 14)

7.6

8.2

8.8

V

Vphi2

Internal Clamping Levels on 2nd PLL

Loop Filter (Pin 4)

Low Level

High Level

1.6

4.2

V

V

VSCinh

VSCinh will stop H-Out, V-Out, B-Out and

reset X-RAY)

Pin 29

7.5

V

HDvd

Horizontal Drive Output (low level)

0.4

V

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units