TDA9111 datasheet(25/43 Pages) STMICROELECTRONICS

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TDA9111

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The last feature performed is the removal of these

equalization pulses which fall in the middle of a

line, to avoid parasitic pulses on the phase compa-

rator (which would be disturbed by missing or ex-

traneous pulses). This last feature is switched on/

off by sub-address 0F D8. By default [0], equaliza-

tion pulses will not be removed.

2.2 PLL1

The PLL1 consists of a phase comparator, an ex-

ternal filter and a voltage-controlled oscillator

(VCO).The phase comparator is a “phase/frequen-

cy” type designed in CMOS technology. This kind

of phase detector avoids locking on wrong fre-

quencies. It is followed by a “charge pump”, com-

posed of two current sources : sunk and sourced

(typically I =1 mA when locked and I = 140

µA

when unlocked). This difference between lock/un-

lock allows smooth catching of the horizontal fre-

quency by PLL1. This effect is reinforced by an in-

ternal original slow down system when PLL1 is

locked, avoiding the horizontal frequency chang-

ing too quickly. The dynamic behavior of PLL1 is

fixed by an external filter which integrates the cur-

rent of the charge pump. A “CRC” filter is generally

used (see Figure 7 on page 25).

Figure 7.

The PLL1 is internally inhibited during extracted

vertical sync (if any) to avoid taking in account

missing pulses or wrong pulses on phase compa-

rator. Inhibition is obtained by stopping high and

low signals at the input of the charge pump block

(see Figure 8 on page 25).

Figure 8.

PLL1F

1.8k

Ω

10nF

Extracted

Lock/Unlock

Status

VSync

PLL

INHIBITION

HPOSITION

PHASE

ADJUST

Low

High

LOCKDET

COMP1

CHARGE

PUMP

PLL1F

VCO

OSC

I2C

HPOS

Adj.

Extracted

VSync

INPUT

INTERFACE

H/HVIN

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