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TDA9111 数据表(PDF) 24 Page - STMicroelectronics |
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TDA9111 数据表(HTML) 24 Page - STMicroelectronics |
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24 / 43 page ![]() TDA9111 24/43 In order to choose the right sync priority the MCU may proceed as follows (see I2C Address Table): – refresh the status register, – wait at least for 20ms (Max. vertical period), – read this status register. Sync priority choice should be : Of course, when the choice is made, we can re- fresh the sync detections and verify that the ex- tracted Vsync is present and that no sync type change has occurred. The sync processor also gives sync polarity information. 1.7 IC status The IC can inform the MCU about the 1st horizon- tal PLL and vertical section status (locked or not) and about the XRAY protection (activated or not).Resetting the XRAY internal latch can be done either by decreasing the VCC supply or di- rectly resetting it via the I 2C interface. 1.8 Sync Inputs Both H/HVIN and VSYNCIN inputs are TTL com- patible triggers with hysteresis to avoid erratic de- tection. Both inputs include a pull up resistor con- nected to VDD. 1.9 Sync Processor Output The sync processor indicates on the D8 bit of the status register whether 1st PLL is locked to an in- coming horizontal sync. Its level goes to low when locked. This information is also available on pin 3 if sub-address 02 D8 is equal to 1. When PLL1 is un- locked, pin 3 output voltage becomes greater than 6V. When it is locked, the HMoiré waveform is available on pin 3 (max voltage: 3V). 2 HORIZONTAL PART 2.1 Internal Input Conditions A digital signal (horizontal sync pulse or TTL com- posite) is sent by the sync processor to the hori- zontal input. It may be positive or negative (see Figure 5). Using internal integration, both signals are recog- nized if Z/T < 25%. Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7 µs. Another integration is able to extract the vertical pulse from composite sync if the duty cycle is high- er than 25% (typically d = 35%), (see Figure 6). Figure 5. Figure 6. Vextd et H/V det V det Sync priority Subaddress 03 (D8) Comment Sync type No Yes Yes 1 Separated H&V Yes Yes No 0 Composite TTL H&V d CSync Integ. VSyn |
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