TDA9115 datasheet(24/45 Pages) STMICROELECTRONICS

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TDA9115

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Figure 2. Horizontal sync signal

Figure 3. Extraction of V-sync signal from H/V-sync signal

9.2.2 Automatic sync. selection mode

I2C bus bit VSyncAuto is set to 1. In this mode, the

device itself controls the I

2C bus bits switching the

polarity inverters and the vertical sync. signal se-

lector (VSyncSel), using the information provided

by detection circuitry. If both extracted and pure

vertical sync. signals are present, the one already

selected is maintained. No intervention of the

MCU is necessary.

9.3 HORIZONTAL SECTION

9.3.1 General

The horizontal section consists of two PLLs with

various adjustments and corrections, working on

horizontal deflection frequency, then phase shift-

ing and output driving circuitry providing H-drive

signal on HOut pin. Input signal to the horizontal

section is output of the polarity inverter on H/

HVSyn input. The device ensures automatically

that this polarity be always positive.

9.3.2 PLL1

The PLL1 block diagram is in Figure 5. It consists

of a voltage controlled oscillator (VCO), a shaper

with adjustable threshold, a charge pump with inhi-

bition circuit, a frequency and phase comparator

and timing circuitry. The goal of the PLL1 is to

make the VCO ramp signal match in frequency the

sync. signal and to lock this ramp in phase to the

sync. signal, with a possibility to adjust a perma-

nent phase offset. On the screen, this offset re-

sults in the change of horizontal position of the pic-

ture. The loop, by tuning the VCO accordingly,

gets and maintains in coincidence the rising edge

of input sync. signal with signal REF1, which is de-

rived from the VCO ramp by a comparator with

threshold adjustable through

HPOS I2C bus con-

trol. The coincidence is identified and flagged by

lock detection circuit on pin HLckVBk .

The charge pump provides positive and negative

currents charging the external loop filter on HPosF

pin. The loop is independent of the trailing edge of

sync. signal and only locks to its leading edge. By

design, the PLL1 does not suffer from any dead

band even while locked. The speed of the PLL1

depends on the current value provided by the

charge pump. While not locked, the current is very

low, to slow down the changes of VCO frequency

and thus protect the external power components

at sync. signal change. In locked state, the cur-

rents are much higher, two different values being

selectable via PLL1Pump I2C bus bit to provide a

mean to control the PLL1 speed by S/W. Lower

values make the PLL1 slower, but more stable.

Higher values make it faster and less stable. In

general, the PLL1 speed should be higher for high

deflection frequencies. The response speed and

stability (jitter level) depends on the choice of ex-

ternal components making up the loop filter. A

“CRC” filter is generally used (see Figure 4 on

page 25).

Positive

Negative

tPulseHSyn

H/V-sync

Integration

Extracted

textrV

tPulseHsyn

V-sync

Internal

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