TDA9115 datasheet(25/45 Pages) STMICROELECTRONICS

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TDA9115

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Figure 4. H-PLL1 filter configuration

The PLL1 is internally inhibited during extracted

vertical sync. pulse (if any) to avoid taking into ac-

count missing or wrong pulses on the phase com-

parator. Inhibition is obtained by forcing the charge

pump output to high impedance state. The inhibi-

tion

mechanism

can

disabled

through

PLL1Pump I2C bus bit.

The Figure 7, in its upper part, shows the position

of the VCO ramp signal in relation to input sync.

pulse for three different positions of adjustment of

horizontal position control

HPOS.

Figure 5. Horizontal PLL1 block diagram

Figure 6. Horizontal oscillator (VCO) schematic diagram

HPLL1F

Lock

Status

PLL

INHIBITION

HPosF

SHAPER

Low

High

LOCK

COMP

CHARGE

PUMP

HPLL1F R0

VCO

HOSC

(I2C)

HPOS

INPUT

INTERFACE

H/HVSyn

Sync

PLL1Pump

V-sync (extracted)

PLL1InhEn

(I2C)

HOscF

DETECTOR

Polarity

V-sync

Extracted

REF1

(pin & I2C)

(I2C)

PLL1

Flip-Flop

VHOThrHi

4I0

HPLL1F

(PLL1 filter)

HOscF

VHOThrLo

VHOThrHi

from charge pump

VHO

VCO discharge

control

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