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MPC8313VRGDFA 数据表(PDF) 61 Page - Freescale Semiconductor, Inc

部件名 MPC8313VRGDFA
功能描述  PowerQUICC??II Pro Processor Hardware Specifications
PDF  100 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8313VRGDFA 数据表(HTML) 61 Page - Freescale Semiconductor, Inc

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MPC8313E PowerQUICCII Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
61
SPI
17.2
IPIC AC Timing Specifications
Table 60 provides the IPIC input and output AC timing specifications.
18 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8313E.
18.1
SPI DC Electrical Characteristics
Table 61 provides the DC electrical characteristics for the MPC8313E SPI.
18.2 SPI AC Timing Specifications
Table 62 and provide the SPI input and output AC timing specifications.
Table 60. IPIC Input AC Timing Specifications1
Characteristic
Symbol2
Min
Unit
IPIC inputs—minimum pulse width
tPIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working
in edge triggered mode.
Table 61. SPI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
V
Output low voltage
VOL
IOL = 6.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Input high voltage
VIH
—2.1
NVDD +0.3
V
Input low voltage
VIL
–0.3
0.8
V
Input current
IIN
0 V
≤ VIN ≤ NVDD
±5
μA
Table 62. SPI AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
SPI outputs—master mode (internal clock) delay
tNIKHOV
0.5
6
ns
SPI outputs—slave mode (external clock) delay
tNEKHOV
28
ns
SPI inputs—master mode (internal clock) input setup time
tNIIVKH
6—
ns
SPI inputs—master mode (internal clock) input hold time
tNIIXKH
0—
ns
SPI inputs—slave mode (external clock) input setup time
tNEIVKH
4—
ns



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