MPC8313VRGDFA datasheet(63/100 Pages) FREESCALE

63 / 100 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Package and Pin Listings

Figure 55 shows the SPI timing in master mode (internal clock).

Figure 55. SPI AC Timing in Master Mode (Internal Clock) Diagram

19 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8313E is available in

a thermally enhanced plastic ball grid array (TEPBGAII), see Section 19.1, “Package Parameters for the

MPC8313E TEPBGAII,” and Section 19.2, “Mechanical Dimensions of the MPC8313E TEPBGAII,” for

information on the TEPBGAII.

19.1

Package Parameters for the MPC8313E TEPBGAII

The package parameters are as provided in the following list. The package type is 27 mm

× 27 mm,

516 TEPBGAII.

Package outline

27 mm

× 27 mm

Interconnects

516

Pitch

1.00 mm

Module height (typical)

2.25 mm

Solder Balls

95.5 Sn/0.5 Cu/4 Ag (VR package),

62 Sn/36 Pb/2 Ag (ZQ package)

Ball diameter (typical)

0.6 mm

SPICLK (Output)

tNIIXKH

tNIKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

tNIIVKH

MPC8313VRGDFA 数据表(PDF) 63 Page - Freescale Semiconductor, Inc

MPC8313VRGDFA 数据表(HTML) 63 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表下载