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MPC8313VRGDFA 数据表(PDF) 11 Page - Freescale Semiconductor, Inc |
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MPC8313VRGDFA 数据表(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 100 page  MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1 Freescale Semiconductor 11 Power Characteristics Table 5 describes a typical scenario where blocks with the stated percentage of utilization and impedances consume the amount of power described. 1 Table 6 shows the estimated core power dissipation of the MPC8313E while transitioning into the D3 warm low-power state. Table 5. MPC8313E Typical I/O Power Dissipation Interface Parameter GVDD (1.8 V) GVDD (2.5 V) NVDD (3.3 V) LVDDA/ LVDDB (3.3 V) LVDDA/ LVDDB (2.5 V) LVDD (3.3 V) Unit Comments DDR 1, 60% utilization, 50% read/write Rs = 22 Ω Rt = 50 Ω single pair of clock capacitive load: data = 8 pF, control address = 8 pF, clock = 8 pF 333 MHz, 32 bits — 0.355 —— —— W — 266 MHz, 32 bits — 0.323 —— —— W — DDR 2, 60% utilization, 50% read/write Rs = 22 Ω Rt = 75 Ω single pair of clock capacitive load: data = 8 pF, control address = 8 pF, clock = 8 pF 333 MHz, 32 bits 0.266 — — — — — W — 266 MHz, 32 bits 0.246 — — — — — W — PCI I/O load = 50 pF 33 MHz — — 0.120 — — — W — 66 MHz — — 0.249 — — — W — Local bus I/O load = 20 pF 66 MHz — — — — — 0.056 W — 50 MHz — — — — — 0.040 W — TSEC I/O load = 20 pF MII, 25 MHz — — — 0.008 — — W Multiple by number of interface used RGMII, 125 MHz — — — 0.078 0.044 — W USBDR controller load = 20 pF 60 MHz — — — 0.078 — — W — Other I/O — — — 0.015 — — — W — Table 6. MPC8313E Low-Power Modes Power Dissipation1 1 All interfaces are enabled. For further power savings, disable the clocks to unused blocks. 333-MHz Core, 167-MHz CSB2 2 The interfaces are run at the following frequencies: DDR: 333 MHz, eLBC 83 MHz, PCI 33 MHz, eTSEC1 and TSEC2: 167 MHz, SEC: 167 MHz, USB: 167 MHz. See the SCCR register for more information. Rev. 1.0 3 3 This is maximum power in D3 Warm based on a voltage of 1.05 V and a junction temperature of 105 °C. Rev. 2.x or Later3 Unit D3 warm 400 425 mW |
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