MPC8313ECVRGDDA datasheet(28/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.3

SGMII Interface Electrical Characteristics

Each SGMII port features a 4-wire AC-coupled serial link from the dedicated SerDes interface of

MPC8313E as shown in Figure 15, where CTX is the external (on board) AC-coupled capacitor. Each

output pin of the SerDes transmitter differential pair features a 50-

Ω output impedance. Each input of the

SerDes receiver differential pair features 50-

Ω on-die termination to XCOREVSS. The reference circuit

of the SerDes transmitter and receiver is shown in Figure 33.

When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of

this eTSEC port can be left floating. The input signals should be terminated based on the guidelines

described in Section 22.5, “Connection Recommendations,” as long as such termination does not violate

the desired POR configuration requirement on these pins, if applicable.

When operating in SGMII mode, the TSEC_GTX_CLK125 clock is not required for this port. Instead, the

SerDes reference clock is required on SD_REF_CLK and SD_REF_CLK pins.

8.3.1

DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK

The characteristics and DC requirements of the separate SerDes reference clock are described in Section 9,

“High-Speed Serial Interfaces (HSSI).”

8.3.2

AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK

Table 31 lists the SGMII SerDes reference clock AC requirements. Note that SD_REF_CLK and

SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock

source.

8.3.3

SGMII Transmitter and Receiver DC Electrical Characteristics

Table 32 and Table 33 describe the SGMII SerDes transmitter and receiver AC-coupled DC electrical

characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SD_TX[n] and

SD_TX[n]) as depicted in Figure 16.

Table 31. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typ

Max

Unit

tREF

REFCLK cycle time

—

tREFCJ

REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles

——

100

tREFPJ

Phase jitter. Deviation in edge location with respect to mean

edge location

–50

—

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