MPC8313ECVRGDDA datasheet(41/100 Pages) FREESCALE

41 / 100 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

NOTE

Figure 27 to Figure 30 are for conceptual reference only. Due to the fact that

the clock driver chip's internal structure, output impedance, and termination

requirements are different between various clock driver chip manufacturers,

it is possible that the clock circuit reference designs provided by clock

driver chip vendors are different from what is shown in the figures. They

might also vary from one vendor to the other. Therefore, Freescale can

neither provide the optimal clock driver reference circuits, nor guarantee the

correctness of the following clock driver connection reference circuits. It is

recommended that the system designer contact the selected clock driver

chip vendor for the optimal reference circuits for the MPC8313E SerDes

reference clock receiver requirement provided in this document.

Figure 27 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with MPC8313E SerDes reference clock

input’s DC requirement.

Figure 27. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

Figure 28 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common mode voltage is higher than the MPC8313E SerDes reference clock

input’s allowed range (100 to 400 mV), the AC-coupled connection scheme must be used. It assumes the

LVDS output driver features a 50-

Ω termination resistor. It also assumes that the LVDS transmitter

establishes its own common mode level without relying on the receiver or other external component.

n_REF_CLK

SDn_REF_CLK

Clock Driver

100

Ω Differential PWB Trace

Clock driver vendor dependent

source termination resistor

CLK_Out

HCSL CLK Driver Chip

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

MPC8313E

SerDes Refer.

CLK Receiver

Clock Driver

n_REF_CLK

MPC8313ECVRGDDA 数据表(PDF) 41 Page - Freescale Semiconductor, Inc

MPC8313ECVRGDDA 数据表(HTML) 41 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表下载