MPC8313ECVRGDF datasheet(39/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 23. Receiver of SerDes Reference Clocks

9.2.2

DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC8313E SerDes reference clock inputs is different depending on the

signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described

below.

•

Differential mode

— The input amplitude of the differential clock must be between 400 and 1600 mV differential

peak-to-peak (or between 200 and 800 mV differential peak). In other words, each signal wire

of the differential pair must have a single-ended swing less than 800 mV and greater than

200 mV. This requirement is the same for both external DC-coupled or AC-coupled

connection.

— For external DC-coupled connection, as described in Section 9.2.1, “SerDes Reference Clock

Receiver Characteristics,” the maximum average current requirements sets the requirement for

average voltage (common mode voltage) to be between 100 and 400 mV. Figure 24 shows the

SerDes reference clock input requirement for the DC-coupled connection scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

XCOREVSS. Each signal wire of the differential inputs is allowed to swing below and above

the command mode voltage (XCOREVSS). Figure 25 shows the SerDes reference clock input

requirement for AC-coupled connection scheme.

•

Single-ended mode

— The reference clock can also be single-ended. The SD_REF_CLK input amplitude

(single-ended swing) must be between 400 and 800 mV peak-to-peak (from Vmin to Vmax) with

SD_REF_CLK either left unconnected or tied to ground.

— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 26 shows

the SerDes reference clock input requirement for the single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC or

AC coupled externally. For the best noise performance, the reference of the clock could be DC

Input

Amp

n_REF_CLK

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