MPC8313ECVRGDF datasheet(56/100 Pages) FREESCALE

56 / 100 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

PCI

14 PCI

This section describes the DC and AC electrical specifications for the PCI bus.

14.1

PCI DC Electrical Characteristics

Table 51 provides the DC electrical characteristics for the PCI interface.

14.2

PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus. Note that the PCI_CLK or

PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8313E is configured

as a host or agent device.

Table 52 shows the PCI AC timing specifications at 66 MHz.

Table 51. PCI DC Electrical Characteristics1

Parameter

Symbol

Test Condition

Min

Max

Unit

High-level input voltage

VIH

VOUT ≥ VOH (min) or

0.5

× NVDD

NVDD + 0.3

Low-level input voltage

VIL

VOUT ≤ VOL (max)

–0.5

0.3

× NVDD

High-level output voltage

VOH

NVDD = min, IOH = –100 μA0.9 × NVDD

—V

Low-level output voltage

VOL

NVDD = min, IOL = 100 μA

—

0.1

× NVDD

Input current

IIN

0 V

≤ VIN ≤ NVDD

—

±5

μA

Note:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.

Table 52. PCI AC Timing Specifications at 66 MHz

Parameter

Symbol1

Min

Max

Unit

Notes

Clock to output valid

tPCKHOV

—6.0

Output hold from clock

tPCKHOX

1—

Clock to output high impedance

tPCKHOZ

—14

2, 3

Input setup to clock

tPCIVKH

3.0

—

2, 4

Input hold from clock

tPCIXKH

0—

2, 4

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing

(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference

(K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset

(R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the

PCI 2.3 Local Bus Specifications.

3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

MPC8313ECVRGDF 数据表(PDF) 56 Page - Freescale Semiconductor, Inc

MPC8313ECVRGDF 数据表(HTML) 56 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表下载

链接网址

MPC8313ECVRGDF 数据表(PDF) 56 Page - Freescale Semiconductor, Inc

MPC8313ECVRGDF 数据表(HTML) 56 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表 下载

链接网址

数据表下载