MPC8313ECVRGDF datasheet(78/100 Pages) FREESCALE

78 / 100 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Clocking

The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK,

depending on whether the device is configured in PCI host or PCI agent mode. When the device is

configured as a PCI host device, SYS_CLK_IN is its primary input clock. SYS_CLK_IN feeds the PCI

clock divider (

÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The

CFG_CLKIN_DIV configuration input selects whether SYS_CLK_IN or SYS_CLK_IN/2 is driven out

on the PCI_SYNC_OUT signal. The OCCR[PCICOEn] parameters select whether the PCI_SYNC_OUT

is driven out on the PCI_CLK_OUTn signals.

PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to

synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,

with equal delay to all PCI agent devices in the system, to allow the device to function. When the device

is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured

as a PCI agent device the SYS_CLK_IN signal should be tied to VSS.

As shown in Figure 57, the primary clock input (frequency) is multiplied up by the system phase-locked

loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the

DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbc_clk).

The csb_clk frequency is derived from a complex set of factors that can be simplified into the following

equation:

csb_clk = {PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV)} × SPMF

In PCI host mode, PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV) is the SYS_CLK_IN frequency.

The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up

the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL

multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)

which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,

Clocking, and Initialization,” in the MPC8313E PowerQUICC II Pro Integrated Processor Family

Reference Manual, for more information on the clock subsystem.

The internal ddr_clk frequency is determined by the following equation:

ddr_clk = csb_clk × (1 + RCWL[DDRCM])

Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider

(

÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate

is the same frequency as ddr_clk.

The internal lbc_clk frequency is determined by the following equation:

lbc_clk = csb_clk × (1 + RCWL[LBCM])

Note that lbc_clk is not the external local bus frequency; lbc_clk passes through the a LBC clock divider

to create the external local bus clock outputs (LCLK[0:1]). The LBC clock divider ratio is controlled by

LCCR[CLKDIV].

In addition, some of the internal units may be required to be shut off or operate at lower frequency than

the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped

frequency.

MPC8313ECVRGDF 数据表(PDF) 78 Page - Freescale Semiconductor, Inc

MPC8313ECVRGDF 数据表(HTML) 78 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表下载