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MPC8313ECVRGDF 数据表(PDF) 91 Page - Freescale Semiconductor, Inc |
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MPC8313ECVRGDF 数据表(HTML) 91 Page - Freescale Semiconductor, Inc |
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91 / 100 page ![]() MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1 Freescale Semiconductor 91 System Design Information Figure 60. Driver Impedance Measurement The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value Rterm. The measured voltage is V2 =(1/(1/R1 +1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1/V2 – 1). The drive current is then Isource =V1/Rsource. Table 72 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal NVDD, 105°C. 22.7 Configuration Pin Muxing The MPC8313E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k Ω on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. Table 72. Impedance Characteristics Impedance Local Bus, Ethernet, DUART, Control, Configuration, Power Management PCI Signals (Not Including PCI Output Clocks) PCI Output Clocks (Including PCI_SYNC_OUT) DDR DRAM Symbol Unit RN 42 Target 25 Target 42 Target 20 Target Z0 Ω RP 42 Target 25 Target 42 Target 20 Target Z0 Ω Differential NA NA NA NA ZDIFF Ω Note: Nominal supply voltages. See Table 1, TJ = 105°C. NVDD VSS Pad Data SW1 SW2 RN RP |
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