CS2000-OTP

DS758PP1

21

5.7.2.3

M2 Configured as Auto Fractional-N Source Selection Disable

If M2Config[2:0] is set to ‘100’, M2 becomes a disable pin for the auto fractional-N source selection

functionality. If auto fractional-N source selection is enabled (see section 5.4.6 on page 16), driving

M2 ‘high’ will disable the auto fractional-N source selection and revert control over the fractional-N

source to the FracNSrc modal parameter, regardless of the LockClk[1:0] modal parameter and the

presence of a clock on CLK_IN. If auto fractional-N source selection is not enabled, toggling M2 will

have no effect in this case.

5.7.2.4

M2 Configured as Auto R-Mod Enable

If M2Config[2:0] is set to ‘101’, M2 becomes the Auto R-Mod enable pin and will override the Au-

toRMod modal parameter. If M2 is driven ‘low’, Auto R-Mod will be disabled, if M2 is driven ‘high’

Auto R-Mod will be enabled.

5.7.2.5

M2 Configured as Fractional-N Source Select

If M2Config[2:0] is set to ‘110’, M2 becomes the Fractional-N Source Select pin and will override

the FracNSrc modal parameter. It should be noted that overriding FracNSrc has no effect when

auto clock switching is enabled (see section 5.4.6 on page 16). If M2 is driven ‘low’, the fractional-

is driven ‘high’ the fractional-N value will be the Dynamic Ratio sourced from the Digital PLL for Hy-

brid PLL Mode.

5.7.2.6

M2 Configured as AuxOutSrc Override

If M2Config[2:0] is set to ‘111’, M2 when driven ‘high’ will override the AuxOutSrc[1:0] modal pa-

rameter and force the AUX_OUT source to PLL Clock Output. When M2 is driven ‘low’, AUX_OUT

will function according to AuxOutSrc[1:0].

5.8

Clock Output Stability Considerations

5.8.1

Output Switching

The CS2000-OTP is designed such that re-configuration of the clock routing functions do not result in a

partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or

disabling an output, changing the auxiliary output source between REF_CLK and CLK_OUT, changing

between Frequency Synthesizer and Hybrid PLL Mode, and the automatic disabling of the output(s) dur-

ing unlock will not cause a runt or partial clock period.

The following exceptions/limitations exist:

• Enabling/disabling AUX_OUT when AuxOutSrc = 11 (unlock indicator).

• Switching AuxOutSrc[1:0] to or from 01 (CLK_IN) and to or from 11 (unlock indicator)

(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).

When any of these exceptions occur, a partial clock period on the output may result.