CS2000-OTP

22

DS758PP1

5.8.2

PLL Unlock Conditions

Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the

presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un-

locked:

• Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new

setting takes affect.

• Changes made to the state of the M2 when the M2Config[2:0] global parameter is set to 011, 100, 101,

or 110 can cause the PLL to temporarily lose lock as the new setting takes affect.

• Any discontinuities on the Timing Reference Clock, REF_CLK.

• Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature

is enabled and the requirements of Clock Skipping are satisfied (see “CLK_IN Skipping Mode” on

page 11).

• Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency.

• Step changes in CLK_IN frequency.